1. Field of the Invention
The invention relates to double data rate (DDR) memory, and in particular, to a calibration method for data strobe skew compensation in a DDR memory controller.
2. Description of the Related Art
FIG. 1 shows a conventional memory controller transmitting data utilizing data signal DQ and data strobe signal DQS. A command generator 112 delivers a read command to a memory device (not shown), and the memory device responds data signal DQ and a data strobe signal DQS to the memory controller 102. In the memory controller 102, the data signal DQ and data strobe signal DQS are passed individually through the DQ path 104 and DQS path 106. The DQ path 104 and DQS path 106 are simplified diagrams to represent circuits in the memory controller 102, such as metal, buffers and pads which induce signal latency when passing the data signal DQ and DQS, thus, delayed data signal DQX and compensated data strobe signal DQSX are generated therefrom. Conventionally, data strobe signal DQS is edge-aligned for reading, and center-aligned for writing. Since the DQ path 104 and DQS path 106 induce variable latencies when reading, a delay element 108 is provided to compensate for the latency of compensated data strobe signal DQSX, subsequently aligning the rising edge of the compensated data strobe signal DQSX to the center of delayed data signal DQX. The delay element 108 is controlled by a delay calibration circuit 114 based on a chip internal clock #CLK. The delayed data signal DQX and compensated data strobe signal DQSX are then input to a flip flop 110, and the delayed data signal DQX is sampled by the compensated data strobe signal DQSX to generate output data.
FIG. 2a is a timing chart of transmission latency induced in a memory controller. A rising/falling edge of a data signal DQ consumes a setup time tS, and the voltage level maintains for a hold time tH. The valid data are available for sampling only during the hold time tH. The delayed data signal DQX, having a latency X, is generated from the data signal DQ. The compensated data strobe signal DQSX is generated from the data strobe signal DQS, having a latency Y longer than the latency X, subsequently aligning the rising edge of the compensated data strobe signal DQSX to the center of the holding state of the delayed data signal DQX. The latency Y is adjusted by the delay element 108 under control of the delay calibration circuit 114. Conventionally, the difference between the compensated data strobe signal DQSX and delayed data signal DQX is ¼ cycle time. By aligning the rising edge of compensated data strobe signal DQSX to the center of the delayed data signal DQX, the delayed data signal DQX can be sampled correctly to obtain expected data. The delay calibration circuit 114 compensates latency differences between the output of DQS path 106 and DQ path 104, however, the latencies varies with temperature, circuit mismatch, and wire length, thus, accurate compensation is difficult to achieve, and an effective calibration mechanism to maintain the difference at ¼ cycle time is desirable.
FIG. 2b is a timing chart of a conventional auto refresh cycle. In FIG. 2b, a refresh command #AR is issued to make a memory device (not shown) perform an auto refresh operation occupying a plurality of clock cycles tRFC. During the auto refresh cycle, data strobe signal DQS and data signal DQ are don't care signals, and signals on the command line are null commands NOP. Therefore no data is transmitted by the data signal DQ and data strobe signal DQS during the auto refresh cycle, and this idleness may be wasteful.